The conventional associative memory system, such as a cache memory, is such that information stored in the main memory is previously transferred to an associative memory (hereinafter called "buffer memory") and, then, an associated processor operates by providing access to said buffer memory. If the necessary information is absent in the buffer memory, the necessary information stored in the main memory is loaded in block format into the buffer memory. That is, updating of information in the buffer memory is carried out. The capacity of such associative memory or buffer memory depends upon parameters, such as the set number, the associative level, and the block size of information stored in block format.
According to the concept relating to the buffer memory used in the conventional associative memory system mentioned above, the larger the amount of information that can be transferred to the buffer memory from the main memory at one time, the lesser the possibility that the necessary information will be found to be missing from the buffer memory during the processing operation, resulting in improved overall efficiency of processing. It is, therefore, desirable to design the capacity of the buffer memory to be as large as possible.
To increase the capacity of such a buffer memory in a conventional system the associative level is increased, for the following reason. While usually, a change in the number of sets or in the block size greatly affects the overall processing system, the value of the associative level need not be increased by a power of 2, namely, twice, four times, . . . 2.sup.n times, but can be increased sequentially by twice, thrice, . . . .
However, an increase in the associative levels necessitates a corresponding increase in the number of address comparators required, and complicates the replace circuit used for the updating of information. Also, the addition of one or more address array portions which contain expensive high speed memory elements will become necessary. As for the address array portion in particular, recent superhigh-speed data processing systems employ high-speed elements in the ordinary processing circuits thereof themselves. Meanwhile, the addition of address array portions which require high speed elements having a speed equivalent to that of said elements of an associative memory lead to very high production costs.